1. Field of the Invention
This invention relates to a semiconductor device manufacturing method for connecting interconnects to each other in multilayer interconnection substrates, and more particularly to a semiconductor device manufacturing method effective for multichip modules (MCMs).
2. Description of the Related Art
To make semiconductor devices denser and smaller, multichip packages, where more than one semiconductor chip on which integrated circuit elements and discrete semiconductor elements are formed is squeezed in a single package, have recently been in use. With conventional packaging forms, where many DIPs (dual-in-line packages) or plug-in packages are mounted in a printed circuit board, the faster LSIs cannot achieve their best performance. That is, the delay time cannot be shortened because the interconnection runners between chips are too long in terms of signal propagation delay time. To overcome this drawback, high-performance, high-packing-density multichip modules (MCMs) have been developed in which many semiconductor chips are mounted on a single semiconductor substrate such as a ceramic substrate or a silicon substrate, and the interconnection length between semiconductor chips is made very short. Connecting interconnects to each other on a circuit board or a semiconductor substrate is one of the important manufacturing processes for forming semiconductor devices such as ICs or LSIs. In particular, as semiconductor devices are more highly integrated and made smaller, forming multilayer interconnects on a circuit board and efficiently connecting them are indispensable for the formation of high-performance semiconductor devices.
Referring to FIG. 1, a method of connecting multilayer interconnects on conventional MCM multilayer interconnection substrates will be explained. For example, on a silicon substrate 1 on whose surface a thermal oxide film of 1000 .ANG. thick is formed, a first layer interconnection 2 with a desired pattern is formed. This interconnection 2 has a multilevel structure of Ti/Cu/Ti comprising of two Ti layers of approximately 600 .ANG. thick and a Cu layer of approximately 3 .mu.m thick sandwiched between these two Ti layers. The structure is formed by vapor deposition or sputtering techniques.
Then, for example, a polyimide solution is applied to the entire surface of the semiconductor substrate and dried to form a film. Next, by lithography, a contact hole 31 is made in the film. After this, a non-imido film is calcined to form a polyimide film 3 serving as an interlayer insulating film. Then, on the polyimide film 3, a second layer interconnection 4 of Ti/Cu/Ti, Al, or the like, is formed in a similar manner to the formation of the first layer interconnection 2. At this time, because the second layer interconnection 4 is also formed in the contact hole 31, the first layer interconnection 2 and the second layer interconnection 4 are electrically connected to each other in the contact hole 31. This process is repeated and the interconnects of multilevel layers are connected to one another.
Making the contact hole 31 requires photolithography techniques, etching techniques such as RIE, and such processes as peeling photoresist. Although in the case of polyimide, wet etching can be effected using a choline solution, other organic insulating films must be formed by dry etching. Because the use of wet etching solutions is limited severely, the properties of the films are incompatible with production cost. In addition, as the density of interconnects of the upper layer increases, the upper layer interconnects must be formed on the flat lower-layer surface in a manner that avoids the contact hole in the polyimide film 3 of the lower layer previously formed. This makes it necessary to fill up the contact hole. With this backdrop, the simplification of manufacturing processes is desired.